CMOS circuits are used in a variety of integrated circuit (IC) applications. A CMOS process can be used to fabricate many different sorts of functionality, such as memory, logic, and switching, and thus CMOS techniques are particularly desirable in applications where an IC includes several different types of functional blocks.
One family of ICs employing CMOS fabrication techniques are programmable logic devices (PLDs). PLDs are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device (CPLD). A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In some CPLDs, configuration data is stored on-chip in non-volatile memory. In other CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
For all of these PLDs, the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
IC memory in general, and particularly configuration memory of an FPGA or other PLD, faces several challenges. Generally, configuration memory should provide low ON resistance and high OFF resistance (also known as sensing margin), low leakage current, resistance to single-event upsets (SEUs), and reliable switching operation over a sufficiently high switching cycle lifetime. Micro-electro-mechanical and nano-electro-mechanical (NEM) relays have been proposed for use in configuration memory of FPGAs.
FIG. 1 is a side view of a simplified conventional NEM relay 100. The terminals will be referred to as gate, source, and drain for purposes of convenient discussion, as the NEM relay 100 operates similarly to an FET for switching function. An electrical signal applied to the gate electrode 102 attracts a cantilevered beam 104 indicated by arrow 106 (e.g., by electrostatic attraction), which pulls a contact 108 toward the drain electrode 110, closing an electrical circuit between the drain electrode 110 and the source electrode 112. The cantilevered beam 104 is a conductive material or includes a conductive layer on a suitable beam material. Contact is maintained while the gate electrode 102 is active. When the signal is removed from the gate electrode 102, the cantilevered beam 104 returns to its position of rest and opens the electrical circuit between the source electrode 112 and the drain electrode 110. Alternatively, contact may be maintained by stiction and broken by application of repulsive electrostatic or electromagnetic force.
While such relays provide the desired electrical performance, they do not scale well. As dimensions of NEM relays are reduced, the cantilevered beam(s) become relatively stiffer, and higher voltages are needed to actuate the relays. These higher voltages are not compatible with low-voltage ICs.
Therefore, techniques for providing NEM relays that avoid the problems of the prior art and that reliably scale to smaller dimensions are desirable.